One of the functions of most computers systems is to perform arithmetic operations. Occasionally, an error occurs during an arithmetic operation, often due to malfunction of hardware within the computer system. It is beneficial to detect such an error immediately when it occurs. Traditionally, the detection of such arithmetic errors is performed by providing a duplicate piece of hardware to perform a computation which verifies the main calculation. This can be expensive and potentially very slow.
For instance, in order to detect an addition error the obvious implementation shown in FIG. 1 is to provide an extra full adder 100 to produce the same sum as the original calculation. One would then use an exclusive "NOR" 110 for the width of the result in order to produce a value which indicates whether all of the bits in the first result and the second result were identical. Next, all the bits of the resulting indicator are "AND"ed 120 to generate a single bit result which indicates the success of the operation.
The prime objections to this method are the expense of the full adder 100 and the high propagation delay in performing the full add. Typically, a full adder propagates several outputs including a generate, a propagate, and a compliment of the given result. Once this addition is done there is still the need and expense of performing the exclusive "NOR" and the final "AND" on that result in order to get the single bit answer desired.
It is an object of the present invention to provide a fast and novel method of error detection for arithmetic operations. More particularly, it is an object of this invention to provide such an apparatus and method for detecting errors in a division operation.
It is another object of the present invention to provide a method of error detection which does not require the hardware expense of providing a full adder in the computer system.